1. Field of the Invention
The disclosed embodiments of the present invention relate to verifications of circuit design, and more particularly, to a deadlock detection method for detecting whether deadlock occurs in a circuit path and a related machine readable medium.
2. Description of the Prior Art
Developments in integrated circuit technology go hand in hand with the number of transistors accommodated in an integrated circuit, in accordance with Moore's Law. As both the size and complexity of integrated circuits grows, design verification for ensuring consistency between the design and the specification has become the biggest challenge in the field of integrated circuit design. Static verification is faster; static verification, however, only detects potential errors or defects in a design, but cannot verify the design in every aspect with high assurance, especially the functionality. While simulations can accurately reflect circuit behavior in a real chip, large designs make simulations time-consuming, especially in a digital/analog mixed-signal circuit design. Hence, an IC designer usually performs simulation and validation upon each circuit module separately to obtain enough simulation results within a reasonable simulation time. Although such practices can quickly obtain the functional verification of each circuit module, there could be deadlock between circuit modules. A condition where each circuit module operates normally but deadlock occurs between respective circuit modules will not be detected by the above mentioned simulation process. In conventional processes, the only solution is good communication between circuit designers and manual examiners, which is not only imprecise but also inefficient.
For meeting the demands of efficiency and accuracy, there is a need for an innovative deadlock detection method that can perform verifications upon a complete circuit system containing all of the circuit modules.